Key Features

» Supports provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the P1394a 2000
» Full P1394a Supplement Support includes
  - Arbitrated short reset
  - Enhanced priority arbitration
  - Connection debounce
  - Multispeed packet concatenation
  - Ack accelerated arbitration
  - Fly-by concatenation
  - Per port disable, suspend, resume, through register write and remote command packet
  - Remote access packet
  - Boundary node short reset
  - No phy_ID wrap past 63
» Integrated 400Mbps 2-port PHY
  - Supports two 1394a fully compliant cable ports at 100/200/400Mbps
  - Supports IEEE 1394-1995 Standard for High Performance Serial Bus 1.0 and 1394a P2000
  - Full 1394a P2000 support
  - Logic performs bus initialization and arbitration functions
  - 2KV ESD protection
» Provides two 1394a fully compliant cable ports at 100/200/400 Mbit per second and available with one, two ports
» Single 3.3 V power supply
» Logic performs bus initialization and arbitration functions
» Encode and decode functions included for data-strobe bit-level encoding
» Incoming data resynchronized to local clock.
» Data interface to Link-Layer Controller provided through 2/4/8 parallel lines at 49.152 Symbol/Sec
» 24.576 MHz crystal oscillator provides TX/RX data at 100/200/400 Mbps and Link-Layer Controller clock at 49.152 MHz.
» Cable power presence monitoring
» Programmable node power class information for system power management
» Compliant with Open HCI requirements
» Separate cable bias (TPBIAS) and driver termination voltage supply for each port
» Fully interoperable with IEEE Std1394-1995 devices
» Cable ports monitor line conditions for active connection to remote node
» Automatic power down inactive circuit and logic for low power application
» Self power up reset
» 48-pin LQFP package
» Automatic configuration to single-port and two-port applications; the unused ports are power down automatically
» Easy configured as a repeater