How It Works
In modern digital devices, high frequency clocks required for operation are generated by a specialized device called a Phase-Lock Loop (PLL). In a traditional processor, the frequency of the processor generated by the PLL is fixed once activated, and stays at that frequency until powered down. The latest mobile processors, however, integrate technologies which allow the processor to vary in frequency and voltage based on the system demands placed upon the processor which is controlled by an internal function called "P states".
A significant limitation of competitor mobile processors is that in order for those processors to change frequency due to a change in P states, the processor must suspend all operations, unlock the PLL, move the PLL to the new frequency, relock the PLL, and resume operations in the processor. In the case of the Intel® Pentium® M processor, this operation causes it to effectively pause for roughly 15,000 clock cycles.
The VIA C7-M processor with VIA TwinTurbo technology delivers a unique solution to this problem that integrates two phase lock loops, effectively eliminating any transitional delay. When the processor changes P states, as controlled by VIA PowerSaver technology, the processor will continue to operate at the frequency of the first PLL, while the second PLL will move to the required frequency dictated by the P state. The VIA C7-M processor can then jump from the frequency of the first PLL, to the new frequency of the second PLL in one clock cycle, completely eliminating the transition delay experienced by competitors' implementations. |