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The VIA Isaiah Architecture

The VIA Isaiah Architecture is a new x86 processor architecture that will deliver significant boosts to the functionality and performance of desktop, mobile and ultra mobile PCs while minimizing power requirements, saving on battery life and enabling ultra compact system designs.

Designed from the ground up by the company's US-based processor design subsidiary, Centaur Technology Inc., the VIA Isaiah Architecture combines all the latest advances in x86 processor technology, including a 64-bit superscalar speculative out-of-order microarchitecture, high-performance multimedia computation, and a new virtual machine architecture.

Key Architectural Features

64-bit Next Generation Architecture
The superscalar, speculative out-of-order 'Isaiah, architecture of the VIA Nano processor family supports a full 64-bit instruction set and provides for macro-fusion and micro-fusion functionality, and sophisticated branch prediction for greater processor efficiency and performance.

High-Performance Computation and Media Processing
VIA Nano processors utilize the high-speed, low power VIA V4 Front Side Bus up to 800MHz, while support for new SSE instructions and two 64KB L1 caches and 1MB exclusive L2 cache with 16-way associativity give a big boost to multimedia performance.

In particular, the VIA Nano processor places significant emphasis on high-performance floating-point execution, using a completely new algorithm for floating-point adds that results in the lowest floating-point add latency of any x86 processor. Similarly, the floating-point multiplier has the lowest latency of any x86 processor.

In practical terms, this means the VIA Nano processor provides exceptionally smooth play back of Blu-ray Disc™ and other HD video formats, which can have encrypted media streams of up to 40Mbps, and low latency rendering of 3D images for an excellent PC gaming experience.

Advanced Power and Thermal Management

Aggressive management of active power includes support for the new "C6" power state, Adaptive PowerSaver™ Technology, new circuit techniques and mechanisms for managing the die temperature, reducing power draw and improving thermal management.

Through the above innovations in processor architecture, the VIA Nano processor is able to offer the significant performance improvements that come with the new superscalar architecture, within the same low power envelope of the VIA C7 processor.

Initial production versions of the 1.0 GHz VIA Nano ULV processor will have a maximum Thermal Design Power (TDP) of just 5 watts (and an idle power of just 100mW), scaling up to 25 watts for the 1.8 GHz VIA Nano processor (500mW idle power).

An increase in computational performance, coupled with maintenance of the power envelope has naturally resulted in a greatly improved performance per watt. The VIA Nano processor is easily the leading processor in terms of performance per watt on the market.

To find out more about the advanced thermal management of the VIA Nano processor, you can view an architectural overview here.

Scalable Upgrade to VIA C7® Processor
Pin-to-pin compatibility with current VIA C7 processors enables a smooth transition for OEMs and mainboard vendors, enabling them to offer a wider range of products for different markets with a single board or system design.

Greener Technology
In addition to full compliance with RoHS and WEEE regulations, product manufacturing will be halogen-free and lead-free at launch, helping to promote a cleaner environment and more sustainable computing.

Enhanced VIA PadLock™ Security Engine

The VIA Nano processor continues the VIA processor family's leadership in on-die hardware cryptographic acceleration and security features, and includes dual quantum random number generators, an AES Encryption Engine, NX bit, and SHA-1 and SHA-256 hashing.


  AMD Phenom Intel Core2 Intel Atom VIA C7 VIA Nano
Secure Hash No No No Full SHA-1 & SHA-256
5Gb/s peak
Full SHA-1 & SHA-256
5Gb/s peak
Buffer Overflow NX Bit NX Bit NX Bit NX Bit NX Bit
On-Die Encryption No No No Full AES en/decryption RSA acceleration CBC, CFB-M, AC, CTR modes 25Gb/s peak Full AES en/decryption RSA acceleration CBC, CFB-M, AC, CTR modes 25Gb/s peak
Random Number Generation (RNG) No No No 2 Enhanced Hardware RNGs up to 12Mb/s
Feeds output to SHA engine
2 Enhanced Hardware RNGs up to 12Mb/s
Feeds output to SHA engine
Learn more about the VIA PadLock Security Engine...

Download the introductory white paper for a more in-depth look at the VIA Nano processor family

For more technical information about the VIA Isaiah Architecture, including key design concepts and architectural details, please download the white paper here.

Image files and a presentation of the new Isaiah Architecture can be found here.

To view a video of Glenn Henry, President of Centaur Technology introducing the VIA Isaiah Architecture go here.

Media reaction to the VIA Isaiah Architecture may be viewed here.


VIA Isaiah Architecture Block Diagram

VIA Isaiah Architecture Block Diagram


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